1. Field of the Invention
The present invention relates to an internal bus testing device and method for a semiconductor integrated circuit, such as a microcontroller.
2. Description of the Related Art
In recent years, various functions and advanced features are demanded for semiconductor integrated circuits such as a microcontroller, and the circuit configuration has become increasingly complicated. For this reason, the process of test verification of semiconductor integrated circuits has also become complicated and the time for performing the test verification is increasing.
As the countermeasure against the problem, a built-in testing circuit for a microcontroller is provided as an internal element of the microcontroller, and it is common to perform test verification using the built-in testing circuit. However, the addition of a testing circuit to the microcontroller will lead to the increase of the chip area or the circuit scale.
On the other hand, making the chip area and the circuit scale small is needed to reduce the cost of the semiconductor integrated circuit. Hence, there is an increasing demand for an semiconductor integrated circuit that is capable of performing by itself the internal bus testing efficiently without using any complicated circuit.
FIG. 1 shows an internal bus testing device for a conventional semiconductor integrated circuit.
In FIG. 1, a microcontroller is assumed as an example of the conventional semiconductor integrated circuit incorporating the internal bus testing device.
The internal bus testing device, shown in FIG. 1, is comprised of a plurality of modules including a CPU 1, an internal bus (IN/BUS) control circuit 2, a direct memory access (DMA) controller 3, an internal memory 4 such as a flash memory, and an external bus (EX/BUS) interface 5.
As shown in FIG. 1, the internal bus testing device includes the plurality of modules which are interconnected by a plurality of internal buses. Specifically, the CPU 1 and the internal bus control circuit 2 are interconnected by the instruction bus (I-BUS) 6 and the data bus (D-BUS) 7. The internal bus control circuit 2 and the internal memory 4 are connected by the internal-memory bus (F-BUS) 8. The internal bus control circuit 2 and the external bus interface 5 are interconnected by the external bus (X-BUS) 9. Furthermore, the internal bus control circuit 2 and the DMA controller 3 connected by the DMA bus (M-BUS) 10. Each of the plurality of internal buses includes the address bus, the data bus, and the control signal bus respectively.
Moreover, in the internal bus testing device of FIG. 1, a lead wire from the port 11 is coupled to an input of the external bus interface 5, and the CPU 1 can receive via the external bus 9 an instruction that is externally supplied to the external bus interface 5 via the port 11.
In the internal bus testing device of FIG. 1, the internal bus control circuit 2 controls the respective internal buses. The CPU 1, the DMA controller 3, and the external bus interface 5 can function as a master module to the related one of the internal buses. When the CPU 1 functions as a master module, the internal memory 4 functions as a slave module to the F-BUS 8 and the external bus interface 5 functions as a slave module to the X-BUS 5.
When the CPU 1 functions as the master module to access a certain module from the related internal bus, it is possible for the internal bus testing device to change the address area of the related internal bus during the internal bus testing. For example, when the CPU 1 accesses from the data bus 7 as the master module, it is possible to change the address area in accordance with a predetermined testing pattern “0h→5h→Fh→Ah→0h”. This internal bus testing generally is performed for improvement in the error detection ratio of the semiconductor integrated circuit.
However, in the conventional microcontroller, the access area or destination for each of the plurality of modules is predetermined or fixed for each of the respective internal buses linked to the modules of the internal bus testing device. During the normal operation, it is impossible for the internal bus control circuit 2 to carry out the test verification of several upper-rank bits of the address bus of the related internal bus in the case of outputting the access signal to the slave module. This is because the access area is fixed.
FIG. 10 shows an example of a memory map used by the conventional microcontroller.
In the example of FIG. 10, the address area of 0000—0000h to 0000_FFFFh in the memory map is assigned for the input/output (IO) area 100. The address area of 0001—0000h to 0001_FFFFh is assigned for the I-BUS area 102 corresponding to the instruction bus 6. The address area of 0002—0000h to 0003_FFFFh is assigned for the D-BUS area 104 corresponding to the data bus 7. The address area of 0004—0000h to 000F_FFFFh is assigned for the F-BUS area 106 corresponding to the internal-memory bus 8. The address area of 0010—0000h to FFFF_FFFFh is assigned for the X-BUS area 108 corresponding to the external bus 9.
As described above, in the conventional microcontroller, the access area for each of the respective modules is predetermined for each of the respective internal buses linked to the modules of the internal bus testing device. For example, the address area for the F-BUS 8 is fixed to 000F_FFFFh from 0004—0000h in the conventional semiconductor integrated circuit, and if the internal bus control circuit 2 during the normal operation outputs the access signal through the F-BUS 8 to the internal memory 4 as the slave module, several upper-rank bits of the address bus contained in the F-BUS 8 are meaningless, and the test verification of such bits of the related internal bus is impossible.
In order to perform the above-described internal bus testing, many of conventional semiconductor integrated circuits are provided with a complicated circuit for execution of a test mode. And during the test mode operation, the internal bus testing must be carried out by externally supplying a control signal from external testing equipment to control the internal bus. Therefore, it has been difficult for the user to perform the internal bus testing of the semiconductor integrated circuit by using the actual CPU instructions.